Many modern electronic chips undergo extensive debugging tests to identify and fix bugs and to increase reliability. Debugging protocols such as the Joint Test Action Group (JTAG) architecture have provided standardized systems that enable comprehensive debugging capabilities. JTAG and other similar debugging protocols generally call for the inclusion of various external pins on the periphery of a chip in addition to the inclusion of a debugging controller inside of the chip. A user or tester can then feed debugging test data and instructions to the internal debugging controller via the external pins. The debugging controller then passes the test data into the core logic of the chip according to the specified instructions and captures the output data. Evaluation of the output data can then assist in identifying bugs and other irregularities in the core logic.